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19-6026; rev 5; 9/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max11129.related . sampleset and autoshutdown are trademarks of maxim integrated products, inc . qspi is a trademark of mot orola, inc. microwire is a registered trademark of national semiconductor corporation. general description the max11129Cmax11132 are 12-/10-bit with external reference and industry-leading 1.5mhz, full linear band - width, high speed, low-power , serial output successive approximation register (sar) analog-to-digital convert - ers (adcs). the max11129Cmax11132 include both internal and external clock modes. these devices feature scan mode in both internal and external clock modes. the internal clock mode features internal averaging to increase snr . the external clock mode features the sampleset k technology, a user-programmable analog input channel sequencer. the sampleset approach provides greater sequencing flexibility for multichannel applications while alleviating significant microcontroller or dsp (controlling unit) communication overhead. the internal clock mode features an integrated fifo allowing data to be sampled at high speeds and then held for readout at any time or at a lower clock rate. internal averaging is also supported in this mode improving snr for noisy input signals. the devices feature analog input channels that can be configured to be single-ended inputs, fully differential pairs, or pseudo-differential inputs with respect to one common input. the max11129C max11132 operate from a 2.35v to 3.6v supply and con - sume only 15.2mw at 3msps. the max11129Cmax11132 include autoshutdown k , fast wake-up, and a high-speed 3-wire serial interface. the devices feature full power-down mode for optimal power management. the 48mhz, 3-wire serial interface directly connects to spi, qspi k , and microwire m devices without external logic. excellent dynamic performance, low voltage, low power, ease of use, and small package size make these convert - ers ideal for portable battery-powered data-acquisition applications, and for other applications that demand low power consumption and small space. the max11129Cmax11132 are available in 28-pin, 5mm x 5mm, tqfn packages and the max11131 is available in a 28-pin tssop package. all devices operate over the -40 n c to +125 n c temperature range. benefits and features s scan modes, internal averaging, and internal clock s 16-entry first-in/first-out (fifo) s sampleset: user-defined channel sequence with maximum length of 256 s analog multiplexer with true differential track/hold ? 16-/8-channel single-ended ? 8-/4-channel fully-differential pairs ? 15-/8-channel pseudo-differential relative to a common input s two software-selectable bipolar input ranges ? q v ref+ /2, q v ref+ s flexible input configuration across all channels s high accuracy ? q 1 lsb inl, q 1 lsb dnl, no missing codes over temperature range s 70db sinad guaranteed at 500khz input frequency s 1.5v to 3.6v wide range i/o supply ? allows the serial interface to connect directly to 1.8v, 2.5v, or 3.3v digital systems s 2.35v to 3.6v supply voltage s longer battery life for portable applications ? low power ? 15.2mw at 3msps with 3v supplies ? 2a full-shutdown current s external differential reference (1v to v dd ) s 48mhz, 3-wire spi-/qspi-/microwire-/dsp- compatible serial interface s wide -40 n c to +125 n c operation s space-saving, 28-pin, 5mm x 5mm tqfn packages s 3msps conversion rate, no pipeline delay s 12-/10-bit resolution applications high-speed data acquisition systems high-speed closed-loop systems industrial control systems medical instrumentation battery-powered instruments portable systems max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 v dd to gnd ............................................................. -0.3v to +4v ovdd, ain0Cain13, cnvst/ ain14, ref+, ref-/ain15 to gnd ...................... -0.3v to the lower of (v dd + 0.3v) and +4v cs , sclk, din, dout, eoc to gnd ..... -0.3v to the lower of (v ovdd + 0.3v) and +4v dgnd to gnd ...................................................... -0.3v to +0.3v input/output current (all pins) ........................................... 50ma continuous power dissipation (t a = +70 n c) tqfn (derate 34.4mw/ n c above +70 n c) .................. 2758mw tssop (derate 27mw/ n c above +70 n c) ................... 2162mw operating temperature range ........................ -40 n c to +125 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c tqfn junction-to-ambient thermal resistance ( b ja ) ........... 29 n c/w junction-to-case thermal resistance ( b jc ) .................. 2 n c/w tssop junction-to-ambient thermal resistance ( b ja ) ........... 37 n c/w junction-to-case thermal resistance ( b jc ) .................. 2 n c/w absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (n ote 1) electrical characteristics (max11131/max11132) (v dd = 2.35v to 3.6v, v ovdd = 1.5v to 3.6v, f sample = 3msps, f sclk = 48mhz, 50% duty cycle, v ref+ = v dd , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . parameter symbol conditions min typ max units dc accuracy (notes 3 and 4) resolution res 12 bit 12 bits integral nonlinearity inl 1.0 lsb differential nonlinearity dnl no missing codes 1.0 lsb offset error -0.1 4.0 lsb gain error (note 5) +0.3 4.0 lsb offset error temperature coefficient oe tc 2 ppm/ n c gain temperature coefficient ge tc 0.8 ppm/ n c channel-to-channel offset matching 0.5 lsb line rejection psr (note 6) 0.5 2 lsb/v dynamic performance (500khz, input sine wave) (notes 3 and 7) signal-to-noise plus distortion sinad 70 72.2 db signal-to-noise ratio snr 70 72.3 db total harmonic distortion (up to the 5th harmonic) thd -88 -78 db spurious-free dynamic range sfdr 79 90 db intermodulation distortion imd f 1 = 398.4375khz, f 2 = 275.8125khz -85 db maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
3 electrical characteristics (max11131/max11132) (continued) (v dd = 2.35v to 3.6v, v ovdd = 1.5v to 3.6v, f sample = 3msps, f sclk = 48mhz, 50% duty cycle, v ref+ = v dd , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units full-power bandwidth -3db 50 mhz -0.1db 7.5 full-linear bandwidth sinad > 70db 1.5 mhz crosstalk -0.5db below full scale of 492.1875khz sine wave input to the channel being sampled, apply full- scale 398.4375khz sine wave signal to all 15 nonselected input channels -88 db conversion rate power-up time t pu conversion cycle, external clock 2 cycles acquisition time t acq 52 ns conversion time t conv internally clocked (note 8) 2.1 s externally clocked, f sclk = 48mhz, 16 cycles (note 8) 333 ns external clock frequency f sclk 0.48 48 mhz aperture delay 8 ns aperture jitter rms 30 ps analog input input voltage range v ina unipolar (single-ended and pseudo differential) 0 v ref+ v bipolar (note 9) range bit set to 0 -v ref+ /2 v ref+ /2 range bit set to 1 -v ref+ v ref+ absolute input voltage range ain+, ain- relative to gnd -0.1 v ref+ + 0.1 v static input leakage current i ila v ain_ = v dd , gnd -0.1 1.5 f a input capacitance c ain during acquisition time, range bit = 0 (note 10) 15 pf during acquisition time, range bit = 1 (note 10) 7.5 external reference input ref- input voltage range v ref- -0.3 +1 v ref+ input voltage range v ref+ 1 v dd + 50mv v ref+ input current i ref+ v ref+ = 2.5v, f sample = 3msps 110 f a v ref+ = 2.5v, f sample = 0 0.1 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
4 electrical characteristics (max11131/max11132) (continued) (v dd = 2.35v to 3.6v, v ovdd = 1.5v to 3.6v, f sample = 3msps, f sclk = 48mhz, 50% duty cycle, v ref+ = v dd , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units digital inputs (sclk, din, cs , cnvst ) input voltage low v il v ovdd o 0.25 v input voltage high v ih v ovdd o 0.75 v input hysteresis v hyst v ovdd o 0.15 mv input leakage current i in v ain_ = 0v or v dd 0.09 1.0 f a input capacitance c in 3 pf digital outputs (dout, eoc ) output voltage low v ol i sink = 200 f a v ovdd o 0.15 v output voltage high v oh i source = 200 f a v ovdd o 0.85 v three-state leakage current i l cs = v dd - 0.3 1.5 f a three-state output capacitance c out cs = v dd 4 pf power requirements positive supply voltage v dd 2.35 3.0 3.6 v digital i/o supply voltage v ovdd 1.5 3.0 3.6 v positive supply current i dd f sample = 3msps 5.1 6.5 ma f sample = 0 (3msps devices) 2.5 full shutdown 0.0013 0.006 power dissipation normal mode (external reference) v dd = 3v, f sample = 3msps 15.2 mw v dd = 2.35v, f sample = 3msps 10.3 autostandby v dd = 3v, f sample = 3msps 7.3 v dd = 2.35v, f sample = 3msps 4.35 full/ autoshutdown v dd = 3v 3.9 f w v dd = 2.35v 1.7 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
5 electrical characteristics (max11131/max11132) (continued) (v dd = 2.35v to 3.6v, v ovdd = 1.5v to 3.6v, f sample = 3msps, f sclk = 48mhz, 50% duty cycle, v ref+ = v dd , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) electrical characteristics (max11129/max11130) (v dd = 2.35v to 3.6v, v ovdd = 1.5v to 3.6v, f sample = 3msps, f sclk = 48mhz, 50% duty cycle, v ref+ = v dd , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units timing characteristics (figure 1) (note 11) sclk clock period t cp externally clocked conversion 20.8 ns sclk duty cycle t ch 40 60 % sclk fall to dout transition t dot c load = 10pf v ovdd = 1.5v to 2.35v 4 16.5 ns v ovdd = 2.35v to 3.6v 4 15 16th sclk fall to dout disable t dod c load = 10pf, channel id on 15 ns 14th sclk fall to dout disable c load = 10pf, channel id off 16 ns sclk fall to dout enable t doe c load = 10pf 14 ns din to sclk rise setup t ds 4 ns sclk rise to din hold t dh 1 ns cs fall to sclk fall setup t css 4 ns sclk fall to cs fall hold t csh 1 ns cnvst pulse width t csw see figure 6 5 ns cs or cnvst rise to eoc low (note 6) t cnv_int see figure 7, f sample = 3msps 1.7 2.4 f s cs pulse width t csbw 5 ns parameter symbol conditions min typ max units dc accuracy (notes 3 and 4) resolution res 10 bit 10 bits integral nonlinearity inl 0.4 lsb differential nonlinearity dnl no missing codes 0.4 lsb offset error 0.3 1.0 lsb gain error (note 5) 0.1 1.2 lsb offset error temperature coefficient oe tc 2 ppm/ n c gain temperature coefficient ge tc 0.8 ppm/ n c channel-to-channel offset matching 0.5 lsb line rejection psr (note 6) 0.2 1.0 lsb/v maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
6 electrical characteristics (max11129/max11130) (continued) (v dd = 2.35v to 3.6v, v ovdd = 1.5v to 3.6v, f sample = 3msps, f sclk = 48mhz, 50% duty cycle, v ref+ = v dd , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units dynamic performance (500khz, input sine wave) (notes 3 and 7) signal-to-noise plus distortion sinad 61 61.5 db signal-to-noise ratio snr 61 61.5 db total harmonic distortion (up to the 5th harmonic) thd -86 -76 db spurious-free dynamic range sfdr 77 86 db intermodulation distortion imd f 1 = 398.4375khz, f 2 = 275.8125khz -83 db full-power bandwidth -3db 50 mhz -0.1db 7.5 mhz full-linear bandwidth sinad > 59db 1.5 mhz crosstalk -0.5db below full-scale of 492.1875khz sine-wave input to the channel being sampled; apply full- scale 398.4375khz sine wave signal to all 15 nonselected input channels -88 db conversion rate power-up time t pu conversion cycle, external clock 2 cycles acquisition time t acq 52 ns conversion time t conv internally clocked (note 8) 2.1 s externally clocked, f sclk = 48mhz, 16 cycles (note 8) 333 ns external clock frequency f sclk 0.48 48 mhz aperture delay 8 ns aperture jitter rms 30 ps analog input input voltage range v ina unipolar (single-ended and pseudo differential) 0 v ref+ v bipolar (note 9) range bit set to 0 -v ref+ /2 +v ref+ /2 range bit set to 1 -v ref+ +v ref+ absolute input voltage range ain+, ain- relative to gnd -0.1 v ref+ + 0.1 v static input leakage current i ila v ain_ = v dd , gnd - 0.1 f a input capacitance c ain during acquisition time, range bit = 0 (note 10) 15 pf during acquisition time, range bit = 1 (note 10) 7.5 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
7 electrical characteristics (max11129/max11130) (continued) (v dd = 2.35v to 3.6v, v ovdd = 1.5v to 3.6v, f sample = 3msps, f sclk = 48mhz, 50% duty cycle, v ref+ = v dd , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units external reference input ref- input voltage range v ref- -0.3 +1 v ref+ input voltage range v ref+ 1 v dd + 50mv v ref+ input current i ref+ v ref+ = 2.5v, f sample = 3msps 110 f a v ref+ = 2.5v, f sample = 0 0.1 f a digital inputs (sclk, din, cs , cnvst ) input voltage low v il v ovdd o 0.25 v input voltage high v ih v ovdd o 0.75 v input hysteresis v hyst v ovdd o 0.15 mv input leakage current i in v ain_ = 0v or v dd 0.09 f a input capacitance c in 3 pf digital outputs (dout, eoc ) output voltage low v ol i sink = 200 f a v ovdd o 0.15 v output voltage high v oh i source = 200 f a v ovdd o 0.85 v three-state leakage current i l cs = v dd -0.3 f a three-state output capacitance c out cs = v dd 4 pf power requirements positive supply voltage v dd 2.35 3.0 3.6 v digital i/o supply voltage v ovdd 1.5 3.0 3.6 v positive supply current i dd f sample = 3msps 5.1 ma f sample = 0 (3msps devices) 2.5 full shutdown 0.0013 0.006 power dissipation normal mode (external reference) v dd = 3v, f sample = 3msps 15.2 mw v dd = 2.35v, f sample = 3msps 10.3 autostandby v dd = 3v, f sample = 3msps 7.3 v dd = 2.35v, f sample = 3msps 4.35 full/ autoshutdown v dd = 3v 3.9 f w v dd = 2.35v 1.7 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
8 electrical characteristics (max11129/max11130) (continued) (v dd = 2.35v to 3.6v, v ovdd = 1.5v to 3.6v, f sample = 3msps, f sclk = 48mhz, 50% duty cycle, v ref+ = v dd , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 2: limits are 100% production tested at t a = +25 n c . limits over the operating temperature range are guaranteed by design. note 3: channel id disabled. note 4: tested in single-ended mode. note 5: offset nulled. note 6: line rejection d (d out ) with v dd = 2.35v to 3.6v and v ref+ = 2.35v. note 7: tested and guaranteed with fully differential input. note 8: conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle. maximum conversion time: 1.91 f s + n x 16 x t osc_max t osc_max = 29.4ns, t osc_typ = 25ns. note 9: the operational input voltage range for each individual input of a differentially configured pair is from v dd to gnd. the operational input voltage difference is from -v ref+ /2 to +v ref+ /2 or -v ref+ to +v ref+ . note 10: see figure 3 (equivalent input circuit). note 11: guaranteed by characterization. parameter symbol conditions min typ max units timing characteristics (figure 1) (note 11) sclk clock period t cp externally clocked conversion 20.8 ns sclk duty cycle t ch 40 60 % sclk fall to dout transition t dot c load = 10pf v ovdd = 1.5v to 2.35v 4 16.5 ns v ovdd = 2.35v to 3.6v 4 15 16th sclk fall to dout disable t dod c load = 10pf, channel id on 15 ns 14th sclk fall to dout disable c load = 10pf, channel id off 16 ns sclk fall to dout enable t doe c load = 10pf 14 ns din to sclk rise setup t ds 4 ns sclk rise to din hold t dh 1 ns cs fall to sclk fall setup t css 4 ns sclk fall to cs fall hold t csh 1 ns cnvst pulse width t csw see figure 6 5 ns cs or cnvst rise to eoc low (note 7) t cnv_int see figure 7, f sample = 3msps 2.1 2.4 f s cs pulse width t csbw 5 ns maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
9 figure 1. detailed serial-interface timing diagram typical operating characteristics (max11131ati+/max11132ati+, t a = +25c, unless otherwise noted.) t css t ch t cp t csh t dot t ds t dh t dod t doe cs sclk din dout 16th clock 1st clock t csbw integral nonlinearity vs. digital output code inl (lsb) -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 digital output code (decimal) 3072 2048 1024 0 4096 max11129 toc01 f sample = 3.0msps differential nonlinearity vs. output code max11129 toc02 digital output code (decimal) dnl (lsb) 3072 2048 1024 -0.5 0 0.5 1.0 -1.0 0 4096 f sample = 3.0msps offset error vs. temperature max11129 toc03 temperature (c) offset error (lsb) 110 95 80 65 50 35 20 5 -10 -25 -2.0 -1.0 0 1.0 2.0 3.0 -3.0 -40 125 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
10 typical operating characteristics (continued) (max11131ati+/max11132ati+, t a = +25c, unless otherwise noted.) gain error vs. temperature max11129 toc04 temperature (c) gain error (lsb) 110 95 80 65 50 35 20 5 -10 -25 -2.0 -1.0 0 1.0 2.0 3.0 -3.0 -40 125 f in (khz) snr and sinad (db) 1200 900 600 300 71.5 72.0 72.5 73.0 73.5 74.0 71.0 0 1500 snr and sinad vs. analog input frequency max11129 toc06 f sample = 3.0msps snr sinad histogram for 30,000 conversions (f sample = 3.0msps) max11129 toc05 output code (decimal) number of occurances 2049 2048 2047 2046 5000 10,000 15,000 20,000 25,000 30,000 35,000 0 2045 5 code hits 29,994 code hits 1 code hit thd vs. analog input frequency max11129 toc07 f in (khz) thd (db) 1200 900 600 300 -95 -90 -85 -80 -100 0 1500 f sample = 3.0msps maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
11 typical operating characteristics (continued) (max11131ati+/max11132ati+, t a = +25c, unless otherwise noted.) sfdr vs. analog input frequency max11129 toc08 f in (khz) sfdr (db) 1200 900 600 300 85 90 95 100 80 0 1500 f sample = 3.0msps 500khz sine-wave input (8192-point fft plot) max11129 toc10 frequency (khz) amplitude (db) 1200 900 600 300 -100 -80 -60 -40 -20 0 -120 0 1500 f sample = 3.0msps f in = 500.0486khz a hd2 = -97.6db a hd3 = -104.3db reference current vs. sampling rate max11129 toc11 f s (ksps) i ref (a) 2500 2000 1500 1000 500 50 100 150 200 0 0 3000 analog supply current vs. temperature max11129 toc12 temperature (c) i vdd (ma) 110 95 80 65 50 35 20 5 -10 -25 3.5 4.0 4.5 5.0 5.5 6.0 3.0 -40 125 f sample = 3.0msps v dd = 3.0v snr vs. reference voltage max11129 toc13 v ref+ (v) snr (db) 3.4 3.0 2.6 2.2 1.8 1.4 70 71 72 73 74 69 1.0 f sample = 3.0msps f in = 500.0486khz thd vs. input resistance max11129 toc09 r in (i) thd (db) 300 200 100 -95 -90 -85 -80 -100 0 400 f sample = 3.0msps f in = 500.0486khz maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
12 pin configurations max11129 max11131 tqfn 16 channel top view 26 27 25 24 10 9 11 ain4 ain6 ain7 ain8 ain9 12 ain3 cs v dd v dd din gnd ref+ 12 eoc 45 67 20 21 19 17 16 15 ain0 ain1 cnvst/ain14 ain13 ain12 ain11 ain5 sclk 3 18 28 8 ain2 ain10 + dout 23 13 ref-/ain15 ovdd 22 14 gnd dgnd max11130 max11132 tqfn 8 channel 26 27 25 24 10 9 11 ain4 ain6 ain7 gnd gnd 12 ain3 cs v dd v dd din gnd ref+ 12 eoc 45 67 20 21 19 17 16 15 ain0 ain1 cnvst gnd gnd gnd ain5 sclk 3 18 28 8 ain2 gnd + dout 23 13 ref- ovdd 22 14 gnd dgnd top view ac86 tssop-28 16 channel 25 4 dgnd ain3 26 3o v dd ain2 27 2 dout ain1 28 1 + eoc ain0 22 7 sclk ain6 23 6 cs ain5 21 8 v dd ain7 20 9 ain8 19 10 gnd ain9 18 11 ref+ ain10 17 12 gnd ain11 16 13 ref-/ain15 ain12 24 5 din ain4 15 14 cnvst/ain14 ain13 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
13 pin description max11129 max11131 (16 channel) tqfn max11131 (16 channel) tssop max11130 max11132 (8 channel) tqfn name function 26, 27, 28, 1C11 1C14 ain0Cain13 analog inputs 26, 27, 28, 1C5 ain0Cain7 analog inputs 12 15 cnvst / ain14 active-low conversion start input/analog input 14 12 cnvst active-low conversion start input 13 16 ref-/ain15 external differential reference negative input /analog input 15 13 ref- external differential reference negative input 14, 16 17, 19 6C11, 14, 16 gnd ground 15 18 15 ref+ external positive reference input. apply a reference voltage at ref+. bypass to gnd with a 0.47 f f capacitor. 17, 18 20, 21 17, 18 v dd power-supply input. bypass to gnd with a 10 f f in parallel with a 0.1 f f capacitors. 19 22 19 sclk serial clock input. clocks data in and out of the serial interface 20 23 20 cs active-low chip select input. when cs is low, the serial interface is enabled. when cs is high, dout is high impedance or three-state. 21 24 21 din serial data input. din data is latched into the serial interface on the rising edge of sclk. 22 25 22 dgnd digital i/o ground 23 26 23 ovdd interface digital power-supply input. bypass to gnd with a 10 f f in parallel with a 0.1 f f capacitors. 24 27 24 dout serial data output. data is clocked out on the falling edge of sclk. when cs is high, dout is high impedance or three- state. 25 28 25 eoc end of conversion output. data is valid after eoc pulls low (internal clock mode only). ep exposed pad. connect ep directly to gnd plane for guaranteed performance. maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
14 functional diagram detailed description the max11129Cmax11132 are 12-/10-bit with external reference and industry-leading 1.5mhz, full linear band - width, high-speed, low-power, serial output successive approximation register (sar) analog-to-digital converters (adc). these devices feature scan mode, internal aver - aging to increase snr, and autoshutdown. the external clock mode features the sampleset technol - ogy, a user-programmable analog input channel sequenc - er. the user may define and load a unique sequencing pattern into the adc allowing both high- and low-frequen - cy inputs to be converted without interface activity. this feature frees the controlling unit for other tasks while lower - ing overall system noise and power consumption. the max11129Cmax11132 includes internal clock. the internal clock mode features an integrated fifo, allowing data to be sampled at high speed and then held for read - out at any time or at a lower clock rate. internal averaging is also supported in this mode improving snr for noisy input signals. all input channels are configurable for sin - gle-ended, fully differential or pseudo-differential inputs in unipolar or bipolar mode. the max11129Cmax11132 operate from a 2.35v to 3.6v supply and consume only 15mw at 3msps. the max11129Cmax11132 include autoshutdown, fast wake-up, and a high-speed 3-wire serial interface. the devices feature full power-down mode for optimal power management. data is converted from analog voltage sources in a variety of channel and data-acquisition configurations. microprocessor ( f p) control is made easy through a 3-wire spi-/qspi-/microwire-compatible serial interface. oscillator adc cs cs sclk din dout cnvst eoc sclk ref+ ref+ ovdd ain0 ain1 ain15 v dd ref- ref- dout i/ p mux control logic and sequencer max11129?max11132 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
15 input bandwidth the adcs input-tracking circuitry features a 1.5mhz small-signal full-linear bandwidth to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adcs sampling rate by using undersampling techniques. anti-alias filtering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest. 3-wire serial interface the max11129Cmax11132 feature a serial interface compatible with spi/qspi and microwire devices. for spi/qspi, ensure the cpu serial interface runs in master mode to generate the serial clock signal. select the sclk frequency of 48mhz or less, and set clock polarity (cpol) and phase (cpha) in the f p control registers to the same value. the max11129Cmax11132 operate with sclk idling high, and thus operate with cpol = cpha = 1. set cs low to latch input data at din on the rising edge of sclk. output data at dout is updated on the falling edge of sclk. a high-to-low transition on cs samples the analog inputs and initiates a new frame. a frame is defined as the time between two falling edges of cs . there is a minimum of 16 bits per frame. the serial data input, din, carries data into the control registers clocked in by the rising edge of sclk. the serial data output, dout, delivers the conversion results and is clocked out by the falling edge of sclk. dout is a 16-bit data word containing a 4-bit channel address, followed by a 12-bit conversion result led by the msb when chan_id is set to 1 in the adc mode control register ( figure 2a ). in this mode, keep the clock high for at least one full sclk period before the cs falling edge to ensure best perfor - mance ( figure 2b ). when chan_id is set to 0 (external clock mode only), the 16-bit data word includes a lead - ing zero and the 12-bit conversion result is followed by 3 trailing zeros ( figure 2c ). in the 10-bit adc, the last 2 lsbs are set to 0. figure 2a. external clock mode timing diagram with chan_id=1 figure 2b. external clock mode timing diagram with chan_id=1 for best performance 23 45 67 8 11 01 11 21 31 41 51 6 9 cs sclk din dout msb msb-1 lsb lsb+1 ch[2] ch[1] ch[0] di[15] di[1] ch[3] di[0] di[14] 23 45 67 8 11 01 11 21 31 41 51 6 9 cs sclk din dout msb msb-1 lsb lsb+1 ch[2] ch[1] ch[0] di[15] di[1] ch[3] di[0] t quiet > t sclk maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
16 figure 2c. external clock mode timing diagram with chan_id=0 single-ended, differential, and pseudo-differential input the max11129Cmax11132 include up to 16 analog input channels that can be configured to 16 single-ended inputs, 8 fully differential pairs, or 15 pseudo-differential inputs with respect to one common input (ref-/ain15 is the common input). the analog input range is 0v to v ref+ in single-ended and pseudo-differential mode (unipolar) and q v ref+ /2 or q v ref+ in fully differential mode (bipolar) depending on the range register settings. see table 7 for the range register setting. unipolar mode sets the differential input range from 0 to v ref+ . if the positive analog input swings below the negative analog input in unipolar mode, the digital output code is zero. selecting bipolar mode sets the differential input range to q v ref+ /2 or q v ref+ depending on the range register settings ( table 7 ). in single-ended mode, the adc always operates in uni - polar mode. the analog inputs are internally referenced to gnd with a full-scale input range from 0 to v ref+ . single-ended conversions are internally referenced to gnd ( figure 3 ). the max11129Cmax11132 feature 15 pseudo differen - tial inputs by setting the pdiff_com bits in the unipolar register to 1 ( table 10 ). the 15 analog input signals inputs are referenced to a dc signal applied to the ref-/ain15. fully differential reference (ref+, ref-) when the reference is used in fully differential mode (refsel = 1), the full-scale range is set by the difference between ref+ and ref-. the output clips if the input signal surpasses this reference range. adc transfer function the output format of the max11129Cmax11132 is straight binary in unipolar mode and twos complement in bipolar mode. the code transitions midway between successive integer lsb values, such as 0.5 lsb, 1.5 lsb. figure 4 and figure 5 show the unipolar and bipolar transfer func - tion, respectively. output coding is binary, with 1 lsb = v ref+ /4096. figure 3. equivalent input circuit 23 45 67 8 11 01 11 21 31 41 51 6 9 cs sclk din dout 0 lsb msb] msb-1 msb-2 di[15] di[1] 0 di[0] di[14] dac comparator dac ainn ainn+1 (gnd) hold maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
17 figure 4. unipolar transfer function for 12-bit resolution internal fifo the max11129Cmax11132 contain a fifo buffer that can hold up to 16 adc results. this allows the adc to handle multiple internally clocked conversions without tying up the serial bus. if the fifo is filled and further conversions are requested without reading from the fifo, the oldest adc results are overwritten by the new adc results. each result contains 2 bytes, with the msb preceded by four leading channel address bits. after each falling edge of cs , the oldest available byte of data is available at dout. when the fifo is empty, dout is zero. external clock in external clock mode, the analog inputs are sampled at the falling edge of cs . serial clock (sclk) is used to per - form the conversion. the sequencer reads in the channel to be converted from the serial data input (din) at each frame. the conversion results are sent to the serial output (dout) at the next frame. internal clock the max11129Cmax11132 operate from an internal oscillator, which is accurate within q 15% of the 40mhz nominal clock rate. request internally timed conversions by writing the appropriate sequence to the adc mode control register ( table 2 ). the wake-up, acquisition, con - version, and shutdown sequences are initiated through cnvst and are performed automatically using the inter - nal oscillator. results are added to the internal fifo. with cs high, initiate a scan by setting cnvst low for at least 5ns before pulling it high ( figure 6 ). then, the max11129Cmax11132 wake up, scan all requested channels, store the results in the fifo, and shut down. after the scan is complete, eoc is pulled low and the results are available in the fifo. wait until eoc goes low before pulling cs low to communicate with the serial interface. eoc stays low until cs or cnvst is pulled low again. do not initiate a second cnvst before eoc goes low; otherwise, the fifo may become corrupted. alternatively, set swcnv to 1 in the adc mode control register to initiate conversions with cs rising edge instead of cycling cnvst ( table 2 ). for proper operation, cs must be held low for 17 clock cycles to guarantee that the device interprets the swcnv setting. a delay is initiated at the rising edge of cs and the conversion is started when the delay times out. upon completing the conversion, this bit is reset to 0 ( figure 7 ). apply a soft reset when changing from internal to external clock mode: reset[1:0] = 10. figure 5. bipolar transfer function for 12-bit resolution 01 23 4 fs fff ffe ffd ffc ffb 000 001 002 003 004 output code (hex) input voltage (lsb) fs = v ref+ zs = 0 1 lsb = 4096 v ref+ fs -1.5 lsb -fs +fs 7ff 7fe 001 000 800 801 ffe output code (hex) input voltage (lsb) zs = 0 +fs = 2 v ref+ fff 0 -fs = 2 -v ref+ 1 lsb = 4096 v ref+ +fs -1.5 lsb -fs +0.5 lsb maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
18 figure 6. internal conversions with cnvst figure 7. internal conversions with swcnv internal oscillator on read data from fifo read data from fifo cnvst cs 1 1 eoc sclk din dout up to n internally clocked acquisitions and conversions t csw 16 16 scan operation and results stored in fifo t cnv_int cs eoc sclk din dout internal oscillator on mode control read data from fifo up to n internally clocked acquisitions and conversions swcnv = 1 t cnv_int (n = 1) 1 1 16 16 scan operation and results stored in fifo maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
19 analog input the max11129Cmax11132 produce a digital output that corresponds to the analog input voltage as long as the analog inputs are within the specified operating range. internal protection diodes confine the analog input volt - age within the region of the analog power input rails (v dd , gnd) and allow the analog input voltage to swing from gnd - 0.3v to v dd + 0.3v without damaging the device. input voltages beyond gnd - 0.3v and v dd + 0.3v forward bias the internal protection diodes. limit the forward diode current to less than 50ma to avoid dam - age to the max11129Cmax11132. echo when writing to the adc configuration register, set echo to 1 in adc configuration register to echo back the configuration data onto dout at time n+1 ( figure 8 , table 6 ). scan modes the max11129Cmax11132 feature nine scan modes ( table 3 ). manual mode the next channel to be selected is identified in each spi frame. the conversion results are sent out in the next frame. the manual mode works with the external clock only. the fifo is unused. repeat mode repeat scanning channel n for number of times and store all the conversion results in the fifo. the number of scans is programmed in the adc configuration register. the repeat mode works with the internal clock only. custom_int and custom_ext in custom_int and custom_ext modes, the device scans preprogrammed channels in ascending order. the chan - nels to be scanned in sequence are programmed in the custom scan0 or custom scan1 registers. a new i/p mux is selected every frame on the thirteenth falling edge of sclk. custom_int works with the internal clock. custom_ext works with the external clock. standard_int and standard_ext in standard_int and standard_ext modes, the device scans channels 0 through n in ascending order where n is the last channel specified in the adc mode control register. a new i/p mux is selected every frame on the thirteenth falling edge of sclk. standard_int works with the internal clock. standard_ext works with the external clock. upper_int and upper_ext in upper_int and upper_ext modes, the device scans channels n through 15/11/7/3 in ascending order where n is the first channel specified in the adc mode control register. a new i/p mux is selected every frame on the thirteenth falling edge of sclk. upper_int works with the internal clock. upper_ext works with the external clock. sampleset the sampleset mode of operation allows the definition of a unique channel sequence combination with maxi - mum length of 256. sampleset is supported only in the external clock mode. sampleset is ideally suited for mul - tichannel measurement applications where some analog inputs must be converted more often than others. the sampleset approach provides greater sequencing flexibility for multichannel applications while alleviating significant microcontroller or dsp (controlling unit) com - munication overhead. sampleset technology allows the user to exploit available adc input bandwidth without need for constant communication between the adc and controlling unit. the user may define and load a unique sequencing pattern into the adc allowing both high- and low-frequency inputs to be converted appropriately with - out interface activity. with the unique sequence loaded figure 8. echo back the configuration data cs din t = n-1 dout configuration data configuration data configuration data configuration data configuration data turn on echo t = nt = n+1 t = n+2 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
20 into adc memory, the pattern may be repeated indefi - nitely or changed at any time. for example, the maximum throughput of max11129C max11132 is 3msps. traditional adc scan modes allow up to 16-channel conversions in ascending order. in this case, the effective throughput per channel is 3msps/16 channel or 187.5ksps. the maximum input frequency that the adc can resolve (nyquist theorem) is 93.75khz. if all 16 channels must be measured, with some chan - nels having greater than 93.75khz input frequency, the user must revert back to manual mode requiring con - stant communication on the serial interface. sampleset technology solves this problem. figure 9 provides a sampleset use-model example. figure 9. sampleset use-model example sample set (depth = 256) 1 st cycle2 nd cycle3 rd cycle4 th cycle5 th cycle6 th cycle7 th cycle8 th cycle9 th cycle potential sampleset pattern channel: entry no.: ain2 / ain3 ain2 / ain3 ain2 / ain3 ain2 / ain3 ain0 ain1 ain0 ain0 ain0 ain0 254 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 5 4 3 2 1 255 256 ain1 ain1 ain1 ain1 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 ain12 ain13 ain14 ain15 120 conversions: ain0 and ain1 135 1 122 123 124 125 256 120 conversions: ain0 and ain1 sampleset repeats: length = 256 100khz 100 cycles 10khz 10 cycles 1khz 1 cycles cs ain0 ain1 2 3 5 7 9 11 13 15 17 19 21 23 25 27 29 4 6 8 10 12 14 16 t s = 1/ f s = 1/ 3m sp s = 33 3.33 ns t s t s f in = 100khz 18 31 20 22 24 26 28 30 32 5s 5s 10s 10s fully differential ain0 analog inputs ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain11 ain12 ain13 ain9 ain10 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
21 averaging mode in averaging mode, the device performs the specified number of conversions and returns the average for each requested result in the fifo. the averaging mode works with internal clock only. scan modes and unipolar/bipolar setting when the unipolar or bipolar registers are configured as pseudo-differential or fully differential, the analog input pairs are repeated in this automated mode. for example, if n is set to 15 to scan all 16 channels and all analog input pairs are configured for fully-differential conversion, the adc converts the channels twice. in this case, the user may avoid dual conversions on input pairs by implementing manual mode or using custom_int or custom_ext scan modes. register descriptions the max11129Cmax11132 communicate between the internal registers and the external circuitry through the spi-/qspi-compatible serial interface. table 1 details the register access and control. table 2 through table 14 detail the various functions and configurations. for adc mode control, set bit 15 of the register code identification to zero. the adc mode control register determines when and under what scan condition the adc operates. to set the adc data configuration, set the bit 15 of the register code identification to one. table 1. register access and control table 2. adc mode control register register name register identification code din data inputs bit 15 bit 14 bit 13 bit 12 bit 11 bit [10:0] adc mode control 0 din din din din din adc configuration 1 0 0 0 0 din unipolar 1 0 0 0 1 din bipolar 1 0 0 1 0 din range 1 0 0 1 1 din custom scan0 1 0 1 0 0 din custom scan1 1 0 1 0 1 din sampleset 1 0 1 1 0 din reserved. do not use. 1 1 1 1 1 din bit name bit default state function reg_cntl 15 0 set to 0 to select the adc mode control register scan[3:0] 14:11 0001 adc scan control register (table 3) chsel[3:0] 10:7 0000 analog input channel select register (table 4). see table 3 to determine which modes use chsel[3:0] for the channel scan instruction. reset[1:0] 6:5 00 reset1 reset0 function 0 0 no reset 0 1 reset the fifo only (resets to zero) 1 0 reset all registers to default settings (includes fifo) 1 1 unused maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
22 table 2. adc mode control register (continued) table 3. adc scan control bit name bit default state function pm[1:0] 4:3 00 power management modes (table 5). in external clock mode, pm[1:0] selects between normal mode and various power-down modes of operation. chan_id 2 0 external clock mode. channel address is always present in internal clock mode. set to 1, dout is a 16-bit data word containing a 4-bit channel address, followed by a 12-bit conversion result led by the msb. swcnv 1 0 set to 1 to initiate conversions with the rising edge of cs instead of cycling cnvst (internal clock mode only). this bit is used for the internal clock mode only and must be reasserted in the adc mode control, if another conversion is desired. 0 0 unused scan3 scan2 scan1 scan0 mode name function 0 0 0 0 n/a continue to operate in the previously selected mode. ignore data on bits [10:0]. this feature is provided so that din can be held low when no changes are required in the adc mode control register. bits [6:3, 1] can be still written without changing the scan mode properties. 0 0 0 1 manual the next channel to be selected is identified in each spi frame. the conversion results are sent out in the next frame. clock mode: external clock only channel scan/sequence: single channel per frame channel selection: see table 4, chsel[3:0] averaging: no 0 0 1 0 repeat scans channel n repeatedly. the fifo stores 4, 8, 12, or 16 conversion results for channel n. clock mode: internal clock only channel scan/sequence: single channel per frame channel selection: see table 4, chsel[3:0] averaging: yes 0 0 1 1 standard_int scans channels 0 through n. the fifo stores n conversion results. clock mode: internal clock channel scan/sequence: n channels in ascending order channel selection: see table 4, chsel[3:0] determines channel n averaging: yes maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
23 table 3. adc scan control (continued) scan3 scan2 scan1 scan0 mode name function 0 1 0 0 standard_ext scans channels 0 through n clock mode: external clock channel scan/sequence: n channels in ascending order channel selection: see table 4, chsel[3:0] determines channel n averaging: no 0 1 0 1 upper_int scans channel n through the highest numbered channel. the fifo stores x conversion results where: x = channel 16Cn 16-channel devices x = channel 8Cn 8-channel devices clock mode: internal clock channel scan/sequence: channel n through the highest numbered channel in ascending order channel selection: see table 4, chsel[3:0] determines channel n averaging: yes 0 1 1 0 upper_ext scans channel n through the highest numbered channel clock mode: external clock channel scan/sequence: channel n through the highest numbered channel in ascending order channel selection: see table 4, chsel[3:0] determines channel n averaging: no 0 1 1 1 custom_int scans preprogrammed channels in ascending order. the fifo stores conversion results for this unique channel sequence. clock mode: internal clock channel scan/sequence: unique ascending channel sequence maximum depth: 16 conversions channel selection: see table 12, custom scan0 register and table 13, custom scan1 register averaging: yes 1 0 0 0 custom_ext scans preprogrammed channels in ascending order clock mode: external clock channel scan/sequence: unique ascending channel sequence maximum depth: 16 conversions channel selection: see table 12, custom scan0 register and table 13, custom scan1 register averaging: no maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
24 table 3. adc scan control (continued) table 4. analog input channel select scan3 scan2 scan1 scan0 mode name function 1 0 0 1 sampleset scans preprogrammed channel sequence with maximum length of 256. there is no restriction on the channel pattern. clock mode: external clock only channel scan/ sequence : unique channel sequence maximum depth: 256 conversions channel selection: see table 4 averaging: no 1 0 1 0 continue to operate in the previously selected mode. ignore data on bits [10:0]. 1 0 1 1 continue to operate in the previously selected mode. ignore data on bits [10:0]. 1 1 0 0 continue to operate in the previously selected mode. ignore data on bits [10:0]. 1 1 0 1 continue to operate in the previously selected mode. ignore data on bits [10:0]. 1 1 1 0 continue to operate in the previously selected mode. ignore data on bits [10:0]. 1 1 1 1 continue to operate in the previously selected mode. ignore data on bits [10:0]. chsel3 chsel2 chsel1 chsel0 selected channel (n) 0 0 0 0 ain0 0 0 0 1 ain1 0 0 1 0 ain2 0 0 1 1 ain3 0 1 0 0 ain4 0 1 0 1 ain5 0 1 1 0 ain6 0 1 1 1 ain7 1 0 0 0 ain8 1 0 0 1 ain9 1 0 1 0 ain10 1 0 1 1 ain11 1 1 0 0 ain12 1 1 0 1 ain13 1 1 1 0 ain14 1 1 1 1 ain15 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
25 table 6. adc configuration register table 5. power management modes power-down mode the max11129Cmax11132 feature three power-down modes. static shutdown the devices shut down when the spm bits in the adc configuration register are asserted ( table 6 ). there are two shutdown options: u full shutdown where all circuitry is shutdown. u partial shutdown where all circuitry is powered down except for the internal bias generator. autoshutdown with external clock mode when the pm_ bits in the adc mode control register are asserted ( table 5 ), the device shuts down at the rising edge of cs in the next frame. the device powers up again at the following falling edge of cs . there are two available options: u autoshutdown where all circuitry is shutdown. u autostandby where all circuitry are powered down except for the internal bias generator. autoshutdown with internal clock mode the device shuts down after all conversions are complet - ed. the device powers up again at the next falling edge of cnvst or at the rising edge of cs after the swcnv bit is asserted. pm1 pm0 mode function 0 0 normal all circuitry is fully powered up at all times. 0 1 autoshutdown the device enters full shutdown mode at the end of each conversion. all circuitry is powered down. the device powers up following the falling edge of cs . it takes 2 cycles before valid conversions take place. the information in the registers is retained. 1 0 autostandby the device powers down all circuitry except for the internal bias generator. the part powers up following the falling edge of cs . it takes 2 cycles before valid conversions take place. the information in the registers is retained. 1 1 unused. bit name bit default state function config_setup 15:11 n/a set to 10000 to select the adc configuration register. refsel 10 0 refsel voltage reference ref- configuration 0 external single-ended ain15 ( for the 16-channel devices) 1 external differential ref- avgon 9 0 set to 1 to turn averaging on. valid for internal clock mode only. set to 0 to turn averaging off. maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
26 table 6. adc configuration register (continued) bit name bit default state function navg[1:0] 8:7 00 valid for internal clock mode only. avgon navg1 navg0 function 0 x x performs 1 conversion for each requested result. 1 0 0 performs 4 conversions and returns the average for each requested result. 1 0 1 performs 8 conversions and returns the average for each requested result. 1 1 0 performs 16 conversions and returns the average for each requested result. 1 1 1 performs 32 conversions and returns the average for each requested result. nscan[1:0] 6:5 00 scans channel n and returns 4, 8, 12, or 16 results. valid for repeat mode only. nscan1 nscan0 function 0 0 scans channel n and returns 4 results. 0 1 scans channel n and returns 8 results. 1 0 scans channel n and returns 12 results. 1 1 scans channel n and returns 16 results. spm[1:0] 4:3 00 static power-down modes spm1 spm0 mode function 0 0 normal all circuitry is fully powered up at all times. 0 1 full shutdown all circuitry is powered down. the information in the registers is retained. 1 0 partial shutdown all circuitry is powered down except for the reference and reference buffer. the information in the registers is retained. 1 1 unused echo 2 0 set to 0 to disable the instruction echo on dout. set to 1 to echo back the din instruction given at time = n onto the dout line at time = n + 1. it takes 1 full cycle for the echoing to begin (figure 8). 1:0 0 unused maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
27 table 7. range register (range settings only applies to bipolar fully differential analog input configurations) adc output as a function of unipolar and bipolar modes the adc scan control register ( table 3 ) determines the adc mode of operation. the unipolar and bipolar regis - ters in table 10 and table 11 determine output coding and whether input configuration is single-ended or fully differential. table 9 details the conversion output for analog inputs, ain0 and ain1. the truth table is consistent for any other valid input pairs (ainn/ainn+1). table 8 shows the appli - cable input signal format with respect to analog input configurations. chsel[3:0] is used for manual, repeat, standard_ext, standard_int, upper_ext, upper_int modes of operation. chscan[15:0] is used for custom_ext and custom_int modes of operation. sampleset mode of operation the sampleset register stores the unique channel sequence length. the sequence pattern is comprised of up to 256 unique single-ended and/or differential conver - sions with any order or pattern. patterns are assembled in 4-bit channel identifier nib - bles as described in table 4 . figure 10 presents the sampleset timing diagram. note that two cs frames are required to configure the sampleset functionality. the first frame indicates the sequence length. the second frame is used to encode the channel sequence pattern. after the sampleset register has been coded ( table 14 ), by the next falling edge of cs , the new sampleset pattern is activated ( figure 10 ). if the pattern length is less than seq_length, the remaining channels default to ain0. if the select pattern length is greater than seq_length, the additional data is ignored as the adc waits for the ris - ing edge of cs . if cs is asserted in the middle of a nibble, the full nibble defaults to ain0. upon receiving the sampleset pattern, the user can set the adc mode control register to begin the conver - sion process where data readout begins with the first sampleset entry. while the last conversion result is read, the adc can be instructed to enter autoshutdown, if desired. if the user wishes to change the sampleset length, a new pattern must be loaded into the adc as described in figure 10 . bit name bit default state function range_setup 15:11 n/a set to 10011 to select the range register range0/1 10 0 set to 0 for ain0/1: + v ref+ /2 set to 1 for ain0/1: + v ref+ range2/3 9 0 set to 0 for ain2/3: + v ref+ /2 set to 1 for ain2/3: + v ref+ range4/5 8 0 set to 0 for ain4/5: + v ref+ /2 set to 1 for ain4/5: + v ref+ range6/7 7 0 set to 0 for ain6/7: + v ref+ /2 set to 1 for ain6/7: + v ref+ range8/9 6 0 set to 0 for ain8/9: + v ref+ /2 set to 1 for ain8/9: + v ref+ range10/11 5 0 set to 0 for ain10/11: + v ref+ /2 set to 1 for ain10/11: + v ref+ range12/13 4 0 set to 0 for ain12/13: + v ref+ /2 set to 1 for ain12/13: + v ref+ range14/15 3 0 set to 0 for ain14/15: + v ref+ /2 set to 1 for ain14/15: + v ref+ 2:0 000 unused maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
28 table 8. analog input configuration and unipolar/bipolar waveforms table 9. adc output as a function of unipolar/bipolar register settings channel selection unipolar register bipolar register function bit name uch0/1 pdiff_com bch0/1 ain0 selection: chsel[3:0] = 0000 chscan0 = 1 0 0 0 ain0 (binary, unipolar) 0 0 1 ain0/1 pair (twos complement, bipolar) 1 0 0 ain0/1 pair (binary, unipolar) 1 0 1 ain0/1 pair (binary, unipolar); unipolar register takes precedence x 1 x ain0 referred to ref-/ain15 (binary, unipolar) ain1 selection: chsel[3:0] = 0001 chscan1 = 1 0 0 0 ain1 (binary, unipolar) 0 0 1 ain0/1 pair (twos complement, bipolar) 1 0 0 ain0/1 pair (binary, unipolar) 1 0 1 ain0/1 pair (binary, unipolar), unipolar register takes precedence x 1 x ain1 referred to ref-/ain15 (binary, unipolar) analog input configuration supported waveforms unipolar/bipolar register setting refsel = 0 refsel = 1 single- ended unipolar (binary coding) table 10. unipolar register: set desired channel(s) to 0 or pdiff_com to 1. counterpart register table 11. bipolar register: set desired channel(s) to 0. fully differential unipolar (binary coding) table 10. unipolar register: set desired channel(s) to 1. counterpart register table 11. bipolar register: set desired channel(s) to 0. fully differential bipolar (2s complement) table 11. bipolar register: set desired channel(s) to 1. counterpart register table 10. unipolar register: set desired channel(s) to 0. ref+ ref+ 2 ref- v in + v in - v in - gn d ref+ range: 1v - v dd ref+ range: 1v - v dd 1v 0v -0.3v ref+ v in + v fs = ref+ range = 0 v fs = 2ref+ range = 1 v fs = ref+ range = 0 v fs = 2ref+ range = 1 ref+ ref- v in + gnd, ain1 5 pdiff_com = 1 ref+ range: 1v - v dd ref+ range: 1v - v dd 1v 0v -0.3v ref+ v in + ref+ ref- v in + v in - v in - gn d ref+ range: 1v - v dd ref+ range: 1v - v dd 1v 0v -0.3v ref+ v in + v in - (dc offset or sinusoid) v in - (dc offset or sinusoid) maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
29 table 10. unipolar register table 11. bipolar register bit name bit default state function uni_setup 15:11 set to 10001 to select the unipolar register. uch0/1 10 0 set to 1 to configure ain0 and ain1 for pseudo-differential conversion. set to 0 to configure ain0 and ain1 for single-ended conversion. uch2/3 9 0 set to 1 to configure ain2 and ain3 for pseudo-differential conversion. set to 0 to configure ain2 and ain3 for single-ended conversion. uch4/5 8 0 set to 1 to configure ain4 and ain5 for pseudo-differential conversion. set to 0 to configure ain4 and ain5 for single-ended conversion. uch6/7 7 0 set to 1 to configure ain6 and ain7 for pseudo-differential conversion. set to 0 to configure ain6 and ain7 for single-ended conversion. uch8/9 6 0 set to 1 to configure ain8 and ain9 for pseudo-differential conversion. set to 0 to configure ain8 and ain9 for single-ended conversion. uch10/11 5 0 set to 1 to configure ain10 and ain11 for pseudo-differential conversion. set to 0 to configure ain10 and ain11 for single-ended conversion. uch12/13 4 0 set to 1 to configure ain12 and ain13 for pseudo-differential conversion. set to 0 to configure ain12 and ain13 for single-ended conversion. uch14/15 3 0 set to 1 to configure ain14 and ain15 for pseudo-differential conversion. set to 0 to configure ain14 and ain15 for single-ended conversion. pdiff_com 2 0 set to 1 to configure ain0Cain14 to be referenced to one common dc voltage on the ref-/ain15. set to 0 to disable the 15:1 pseudo differential mode. 1:0 000 unused. bit name bit default state function bip_setup 15:11 set to 10010 to select the bipolar register. bch0/1 10 0 set to 1 to configure ain0 and ain1 for bipolar fully differential conversion. set to 0 to configure ain0 and ain1 for unipolar conversion mode. bch2/3 9 0 set to 1 to configure ain2 and ain3 for bipolar fully differential conversion. set to 0 to configure ain2 and ain3 for unipolar conversion mode. bch4/5 8 0 set to 1 to configure ain4 and ain5 for bipolar fully differential conversion. set to 0 to configure ain4 and ain5 for unipolar conversion mode. bch6/7 7 0 set to 1 to configure ain6 and ain7 for bipolar fully differential conversion. set to 0 to configure ain6 and ain7 for unipolar conversion mode. bch8/9 6 0 set to 1 to configure ain8 and ain9 for bipolar fully differential conversion. set to 0 to configure ain8 and ain9 for unipolar conversion mode. bch10/11 5 0 set to 1 to configure ain10 and ain11 for bipolar fully differential conversion. set to 0 to configure ain10 and ain11 for unipolar conversion mode. bch12/13 4 0 set to 1 to configure ain12 and ain13 for bipolar fully differential conversion. set to 0 to configure ain12 and ain13 for unipolar conversion mode. bch14/15 3 0 set to 1 to configure ain14 and ain15 for bipolar fully differential conversion. set to 0 to configure ain14 and ain15 for unipolar conversion mode. 2:0 000 unused. maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
30 table 12. custom scan0 register table 13. custom scan1 register table 14. sampleset register bit name bit default state function cust_scan0 15:11 set to 10100 to select the custom scan0 register. chscan15 10 0 set to 1 to scan ain15. set to 0 to omit ain15. chscan14 9 0 set to 1 to scan ain14. set to 0 to omit ain14. chscan13 8 0 set to 1 to scan ain13. set to 0 to omit ain13. chscan12 7 0 set to 1 to scan ain12. set to 0 to omit ain12. chscan11 6 0 set to 1 to scan ain11. set to 0 to omit ain11. chscan10 5 0 set to 1 to scan ain10. set to 0 to omit ain10. chscan9 4 0 set to 1 to scan ain9. set to 0 to omit ain9. chscan8 3 0 set to 1 to scan ain8. set to 0 to omit ain8. 2:0 000 unused. bit name bit default state function cust_scan1 15:11 set to 10101 to select the custom scan1 register. chscan7 10 0 set to 1 to scan ain7. set to 0 to omit ain7. chscan6 9 0 set to 1 to scan ain6. set to 0 to omit ain6. chscan5 8 0 set to 1 to scan ain5. set to 0 to omit ain5. chscan4 7 0 set to 1 to scan ain4. set to 0 to omit ain4. chscan3 6 0 set to 1 to scan ain3. set to 0 to omit ain3. chscan2 5 0 set to 1 to scan ain2. set to 0 to omit ain2. chscan1 4 0 set to 1 to scan ain1. set to 0 to omit ain1. chscan0 3 0 set to 1 to scan ain0. set to 0 to omit ain0. 2:0 000 unused. bit name bit default state function smpl_set 15:11 set to 10110 to select the sampleset register. seq_length 10:3 00000000 8-bit binary word indicating desired sequence length. the equation is: sequence length = seq_length + 1 00000000 = sequence length = 1 11111111 = sequence length = 256 coding: straight binary maximum length: 256 adc conversions 2:0 unused. maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
31 figure 10. sampleset timing diagram applications information how to program modes 1) configure the adc (set the msb on din to 1). 2) program adc mode control (set the msb on din to 0) to begin the conversion process or to control power management features. ? if adc mode control is written during a conversion sequence, the adc finishes the present conver - sion and at the next falling edge of cs initiates its new instruction. ? if configuration data (msb on din is a 1) is written during a conversion sequence, the adc finishes the present conversion in the existing scan mode. however, data on dout is not valid in following frames until a new adc mode control instruction is coded. programming sequence flow chart see figure 11 for programming sequence. layout, grounding, and bypassing for best performance, use pcbs with a solid ground plane. ensure that digital and analog signal lines are separated from each other. do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the adc package. noise in the v dd , ovdd, and ref affects the adcs perfor mance. bypass the v dd , ovdd, and ref to ground with 0.1 f f and 10 f f bypass capacitors. minimize capacitor lead and trace lengths for best supply-noise rejection. choosing an input amplifier it is important to match the settling time of the input amplifier to the acquisition time of the adc. the conver- sion results are accurate when the adc samples the input signal for an interval longer than the input signals worst-case settling time. by definition, settling time is the interval between the application of an input voltage step and the point at which the output signal reaches and stays within a given error band centered on the resulting steady-state amplifier output level. the adc input sampling capacitor charges during the sampling cycle, referred to as the acquisition period. during this acquisition period, the settling time is affected by the input resistance and the input sampling capacitance. this error can be estimated by looking at the settling of an rc time constant using the input capacitance and the source impedance over the acquisition time period. figure 13 shows a typical application circuit. the max4430, offering a settling time of 37ns at 16-bit reso - lution, is an excellent choice for this application. see the thd vs. input resistance graph in the typical operating characteristics . cs sclk din entry 1 write sampleset register define seq_length write adc mode control or continue with additional configuration settings entry 2 entry n = (seq_length) dout 1 1 1 16 load sampleset pattern time between cs falling and rising edge depends in seq_length maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
32 figure 11. adc programming sequence select reference unipolar range select external single-ended external differential 1 0 single-ended or differential select adc configuration register set refsel bit to 0 select adc configuration register set refsel bit to 1 figure out number of channels to use (n) for each adc channel single-ended pseudo- differential fully- differential single-ended pseudo- differential unipolar or bipolar pseudo-differential single-ended bipolar se, psd/fd select unipolar and register set bit pdiff_com to 1 for pseudo- differential selection select unipolar and bipolar register set per channel uch{x}/{x+1} and bch{x}/{x+1} to 0 for single-ended selection select bipolar register set per channel bch{x}/{x+1} to 1 for bipolar fully differential select unipolar register set per channel uch{x}/{x+1} to 1 for unipolar select range register set per channel pair range{x}/{x+1} to 1 qv ref+ select range register set per channel pair range{x}/{x+1} to 0 qv ref+ /2 next channel see figure 12 for each adc channel maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
33 figure 12. adc mode select programming sequence repeat internal/external clock standard-int upper-int custom-int manual adc configuration register set avg on bit to 1 set navg[1:0] to n adc configuration register set avg on bit to 1 set navg[1:0] to n average average average adc configuration register set avg on bit to 1 set navg[1:0] to n adc mode control register set scan[3:0] to 0101 set chsel[3:0] to channel number select the right swcnv bit adc mode control register set scan[3:0] to 0011 set chsel[3:0] to channel number select the right swcnv bit adc mode control register set scan[3:0] to 0010 set chsel[3:0] to channel number select the right swcnv bit adc mode control register set scan[3:0] to 0001 set chsel[3:0] to channel number select the pm[1:0] bits adc mode control register set scan[3:0] to 0100 set chsel[3:0] to channel number adc mode control register set scan[3:0] to 0110 set chsel[3:0] to channel number adc mode control register set scan[3:0] to 1001 set chsel[3:0] to channel number adc mode control register set scan[3:0] to 1000 set chsel[3:0] to channel number sampleset register set seq_depth[7:0] to set channel capture depth follow sampleset register with channel pattern of the same size as sequence depth average adc configuration register set avgon bit to 1 set navg[1:0] to n set custom scan0 register set custom scan1 register set custom scan0 register set custom scan1 register adc configuration register set nscan[1:0] for scan count adc mode control register set scan[3:0] to 0111 set chsel[3:0] to channel number select the right swcnv bit internal external yes yes yes no no yes no yes no yes no yes no yes yes no no yes yes no no yes yes no no standard-ext upper-ext custom-ext sampleset maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
34 choosing a reference for devices using an external reference, the choice of the reference determines the output accuracy of the adc. an ideal voltage reference provides a perfect initial accu - racy and maintains the reference voltage indepen dent of changes in load current, temperature, and time. the following parameters need to be considered in selecting a reference: u initial voltage accuracy u temperature drift u current source capability u current sink capability u quiescent current u noise. the max6033 and max6043 are also excellent reference choices ( figure 13 ). figure 13. typical application circuit max4430 max11129?max11132 max6126 max4430 +5v cpu sclk miso mosi ss input 1 4 3 2 5 1 v dc 100pf 500i -5v 500i 10i 0.1f 10f 0.1f 10f 0.1f 470pf 470pf 10f input 2 cog capacitor cog capacitor 0.1f 10f 1f 0.1f +5v 0.1f v dd v dd agnd ain0 ain1 ain15 ref outf outs gnds 1 2 7 6 4 3 gnd din in nr cs dout sclk ovdd gnd v ovdd 0.1f 10f +5v input 2 4 3 2 5 1 v dc 100pf 500i -5v 500i 10i 0.1f 10f 0.1f 10f maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
35 definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nulled. the static linearity parameters for the max11129Cmax11132 are measured using the end-points method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of 1 lsb or less guarantees no miss - ing codes and a monotonic transfer function. signal-to-noise ratio signal-to-noise ratio is the ratio of the amplitude of the desired signal to the amplitude of noise signals at a given point in time. the larger the number, the better. the theoretical minimum analog-to-digital noise is caused by quantization error and results directly from the adcs resolution (n bits): snr = (6.02 x n + 1.76) db in reality, there are other noise sources besides quantiza - tion noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five harmonics, and the dc offset. total harmonic distortion total harmonic distortion (thd) is expressed as: 2222 2345 1 vvvv thd 20 log v ?? +++ ?? = ?? ?? ?? where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest distor - tion component. full-power bandwidth full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3db for a full-scale input. full-linear bandwidth full-linear bandwidth is the frequency at which the sig - nal-to-noise plus distortion (sinad) is more than 68db. intermodulation distortion any device with nonlinearities creates distortion products when two sine waves at two different frequencies (f1 and f2) are input into the device. intermodulation distortion (imd) is the total power of the im2 to im5 intermodulation products to the nyquist frequency relative to the total input power of the two input tones, f1 and f2. the indi - vidual input tone levels are at -6dbfs. maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
36 ordering information note: all devices are specified over the -40 c to +125 c temperature range. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part pin-package bits speed (msps) no. of channels max11129 ati+ 28 tqfn-ep* 10 3 16 max11130 ati+ 28 tqfn-ep* 10 3 8 max11131 ati+ 28 tqfn-ep* 12 3 16 max11131aui+ 28 tssop-ep* 12 3 16 max11132 ati+ 28 tqfn-ep* 12 3 8 package type package code outline no. land pattern no. 28 tqfn-ep t2855+3 21-0140 90-0023 28 tssop-ep u28e+4 21-0108 90-0146 maxim integrated max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 37 ? 2012 maxim integrated products, inc. the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/11 initial release 1 11/11 updated electrical characteristics , typical operating characteristics global, tables 3 and 9, and other minor corrections. 2C11, 14, 21, 22, 26, 27, 28 2 2/12 updated electrical characteristics , pin configurations , pin description , figure 2a, 2b, 2c captions, figure 6, and the internal clock section. 2, 3, 5, 6, 8, 11, 12, 14C17 3 4/12 released the max11132. 35 4 6/12 released the max11130. 35 5 9/12 added max11131 tssop package. 1, 2, 11, 12, 35 max11129Cmax11132 3msps, low-power, serial 12-/10-bit, 8-/16-channel adcs

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